1. Field of the Invention
The present invention relates to large capacity dynamic random access memory integrated circuits. In particular, the invention relates to an exchangeable hierarchical data line structure for accessing memory cell arrays within the memory circuit which permits elimination of some circuits with the result of a corresponding reduction in the integrated circuit size.
2. Description Of Related Art
Large capacity dynamic random access memories are organized in a hierarchical structures. For example, as described with respect to the present invention the dynamic random access memory includes of sixteen unit circuits, each unit circuit includes sixteen block circuits, each block circuit includes sixteen segments, and each segment include 32 (plus a spare) segment cell array circuits. The segments and block circuits are arranged in a checker board of 256 squares. This form of architecture is referred as a hierarchical architecture. The present invention will be described within the context of a single unit circuit comprised of a plurality of block circuits each having a plurality of segments. Taguchi, et at., in a paper titled "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture" (published in the November 1991 IEEE Journal of Solid-State Circuits, Vol. 26, No. 11) is incorporated herein by reference and describes a hierarchical architecture memory circuit with a single-sided shared sense amplifier. The Taguchi, et at. circuit includes a segment slice comprising a cell array from each of the block circuits. Between every two cell arrays is a row of sense amplifiers shared between the two adjacent cell arrays (e.g., see FIG. 10). The sense amplifier are single sided sense amplifiers shared between adjacent cell arrays (e.g. see description with respect to FIG. 5). Two local data lines run within the row of sense amplifiers. Signals on bit lines within a sense amplifier are transferable between the local data lines and bit lines. The local data lines are couplable to predetermined master data lines. Master data lines are organized into two sets of data lines: an upper set and a lower set. Half of the local data lines are couplable to the upper set of data lines and the other half of the local data lines are couplable to the lower set of data lines. In this way the upper set of data lines are shared by half of the sense amplifiers and the lower set of data lines are shared by the other half of the sense amplifiers. By using the master data lines separated into an upper set of data lines and a lower set of data lines, two cell arrays may be operated simultaneously to provide efficient refresh mode operations or data testing and reduce the active power required compared to a one block per unit activation architecture since twice as many memory cells can be refreshed at a time.
However, in order to achieve higher capacity in the same area (i.e., more integration density) it is desirable to employ a double sided sense amplifier layout shared between adjacent cell arrays as described herein with respect to FIG. 7, and it is desirable to provide a separate row redundancy block to increase the yield in manufacturing circuits. Co-pending U.S. patent application (Ser. No. 08/346,965, filed Nov. 30, 1994 by Kirihata et at.), incorporated herein by reference and entitled "A Random Access Memory Having A Flexible Array Redundancy Scheme", describes advanced redundancy concepts. Co-pending U.S. patent application (Ser. No. 08/346,966, filed Nov. 30, 1994 by Kirihata et at.), incorporated herein by reference and entitled "A Random Access Memory With A Simple Test Arrangement", describes testing of such advanced memory arrays.
Direct replacement of the single ended sense amplifiers with double ended sense amplifiers would result in two problems. First, two separate redundancy blocks would be needed to replace respective defective word line circuits associated with the upper and lower halves. This would tend to reduce replacement efficiency and increase the number of sense amplifiers required resulting a lower yield and a larger integrated circuit area. Secondly, the sense amplifiers placed on the upper and lower boundaries of the cell array areas cannot be shared. Use of double sided sense amplifiers would result in an extra boundary row of sense amplifiers. When the chip architecture is organized into upper and lower halves, this would result in two extra sense amplifier boundaries (i.e., requiring a bigger chip).